1. Field of the Invention
The present invention relates in general to a method of manufacturing high-voltage semiconductor integrated circuit devices. More particularly, this invention relates to a method of manufacturing a junction termination extension (JTE) structure for high-voltage diode devices.
2. Technical Background
High-voltage integrated circuit devices have been widely utilized in the fields of communications and electric machine control, as well as in power supplies and consumer electronics. More widespread utilization of these devices is expected in other fields in the future.
One problem with conventional high-voltage integrated circuit devices is an excessive electric field intensity produced in a region near the reverse-biased P-N junction area. Several measures have been employed in the past to cope with this problem. One of them is the so-called junction termination extension (JTE) technique described in "Increased Avalanche Breakdown Voltage and Controlled Surface Electric Fields Using a Junction Termination Extension (JTE) Technique" by V. A. K. Temple, IEEE Transactions on Electron Devices, Vol. ED-30, pp. 954-957, 1983, the disclosure of which is hereby incorporated herein by reference. This technique has been shown to be able to effectively block against the effects of the electric field, even though in a traverse direction the reverse-biased space-charge region is constrained.
Another related problem, however, should also be considered, namely, the excessive electric field intensity present in the region where the metal interconnection strides the space-charge region. The effect of the metal interconnection on the electric field is dependent upon its distance to the silicon substrate beneath it. Typically, there is an oxide layer present between the metal interconnection and the substrate, with the oxide layer having a thickness of approximately 3-5 .mu.m.
Referring first to FIG. 1, a prior art junction termination extension (JTE) structure, in the form of a diode having high-voltage metal interconnection, is shown. There is a stage-shaped field plate 102 formed on anode 10. The typical length of the field plate 102 is approximately 10 .mu.m, and the distance between field plate 102 and silicon substrate 14 is approximately 1 .mu.m (To emphasize the stage-shaped field plate 102, the figure is not drawn to scale). A P.sup.+ region 16 is in contact with anode 10. Adjacent P.sup.+ region 16 is a lightly doped P.sup.- layer 18. Cathode 12 has a high-voltage metal interconnection 122 which extends parallel to silicon substrate 14 and is spaced therefrom a distance of approximately 3-5 .mu.m. An N.sup.+ region 20 is in contact with cathode 12. Field plate 102 and the metal interconnection 122 are separated from the surface of silicon substrate 14 by a silicon dioxide layer 22.
Due to the fact that metal interconnection 122 carries a high voltage and is disposed above field plate 102, a high intensity electric field occurs at the surface of the silicon substrate 14 in a region below the edge of field plate 102, which region is indicated by arrow 24. The breakdown voltage of the device is severely degraded as a result of the presence of this high intensity electric field, especially in the case when the thickness of the oxide layer below the field plate 102 ands the thickness of the oxide layer below the metal interconnection 122 are both small. Obviously, the smaller the thickness, the greater the degradation of the avalanche breakdown voltage. More detailed descriptions of this phenomena can be found in the paper "Influence of Interconnections onto the Breakdown Voltage of Planar High-Voltage P-N Junctions" by E. Falck et al., IEEE Transactions on Electron Devices, Vol. 40, No. 2, pp. 439-447, 1993, the disclosure of which is hereby incorporated by reference.